1. Field of the Invention
The present invention relates to a shift register apparatus and a method thereof. More particularly, the present invention relates to a shift register apparatus and a method thereof which may improve a utilization reliability of NMOS transistors used for pulling down voltage levels of output scan signals within the shift register apparatus to a low level gate voltage, and may cope with an increasing demand of narrow frame panels.
2. Description of Related Art
Recently, with booming development of the semiconductor technology, portable electronic devices and flat panel displays are widely used. Among various kinds of panel displays, the liquid crystal displays (LCDs) having the features of low operation voltage, no radiation, light-weight, small-size, etc. become popular in the market recently. Accordingly, the LCDs developed by various manufacturers trend to be miniaturization and low cost.
To reduce a fabrication cost of the LCD, under a condition that the LCD panel is fabricated based on an amorphous silicon (a-Si) process, some manufacturers have developed a technique to directly disposed shift registers within a scan driving IC that originally disposed at a scan side of the LCD panel on a glass substrate of the LCD panel. Therefore, the scan driving IC originally disposed at the scan side of the LCD panel can be omitted, so as to save the fabrication cost of the LCD.
FIG. 1 is a circuit block diagram illustrating a conventional shift register 100 directly disposed on a glass substrate of an LCD panel. FIG. 2 is an operation waveform diagram of the shift register 100 of FIG. 1. Referring to FIG. 1 and FIG. 2, first, during a first period t1 within a frame period, when a control unit 101 receives a start pulse STV provided by a timing controller (not shown), or receives a scan signal G(n−1) output from a previous shift register (not shown), the control unit 101 generates two control signals CS1 and CS2 to turn on the NMOS transistor TA and turn off the NMOS transistor TB. Therefore, charges of a high level gate voltage VGH can be stored in a capacitor C during the first period t1.
Next, during a second period t2 within the same frame period, the control unit 101 still generates the two control signals CS1 and CS2 to turn on the NMOS transistor TA and turn off the NMOS transistor TB. However, since the capacitor C has already stored the charges of the high level gate voltage VGH during the first period t1, the voltage level of the control signal CS1 generated by the control unit 101 during the second period t2 can be increased to about twice the high level gate voltage VGH, so as to easily raise the voltage level of the scan signal Gn output from the shift register 100 to the high level gate voltage VGH.
Next, after the second period t2 of the same frame period, the control signals CS1 and CS2 generated by the control unit 101 are respectively stabilized to the low level gate voltage VGL and the high level gate voltage VGH, and are maintain unchanged until the first period t1 and the second period t2 of a next frame period. Therefore, according to the above description, the NMOS transistor TB is only turned off during the first period t1 and the second period t2 of the frame period, and is turned on all the other time, so as to pull down the voltage level of the scan signal Gn output from the shift register 100 to the low level gate voltage VGL.
In such case, the NMOS transistor TB may be aged quickly due to a long time turning on state thereof, and accordingly utilization reliability thereof is decreased. Moreover, a charge trapping effect of the NMOS transistor TB is deteriorate, so that a threshold voltage Vth of the NMOS transistor TB is accelerately increased due to the long time turning on state. Therefore, a capability that the NMOS transistor TB pulls down the voltage level of the scan signal Gn output from the shift register to the low level gate voltage VGL is decreased.
Accordingly, a pixel activated corresponding to the scan signal Gn is liable to be mistaken as a pixel activated corresponding to the scan signal G(n+1) output by a next stage shift register, so that images displayed on the LCD can be abnormal.
To resolve the aforementioned problem, number of the NMOS transistors used for pulling down the voltage level of the scan signal output from the shift register to the low level gate voltage is suggested to be increased, and each of the NMOS transistors is utilized together with a control unit, so that only one NMOS transistor pulls down the voltage level of the scan signal output from the shift register to the low level gate voltage at a same time, so as to resolve the above problem.
FIG. 3 is a circuit block diagram of a shift register 300 which may resolve the problem of the shift register 100 of FIG. 1. In which when the voltage level of the scan signal Gn output from the shift register 300 has to be pulled down to the low level gate voltage VGL, the control units 301a and 301b may work under a separated operation mode to control only one of the NMOS transistors T2 and T6 to pull down the voltage level of the scan signal On output from the shift register 300 to the low level gate voltage VGL at the same time, so as to resolve the problem of the shift register 100.
FIG. 4 is a stress testing diagram for the NMOS transistor TB of the shift register 100 of FIG. 1 and the NMOS transistors T2 and T6 of the shift register 300 of FIG. 3. Referring to FIG. 4, a horizontal axis thereof represents time (hour), a vertical axis thereof represents shifting amounts of the threshold voltages (Vth) of the NMOS transistors TB, T2 and T6 (voltage), wherein the horizontal axis and the vertical axis all apply a log scale. Moreover, a solid line 401 raised along with the time represents a shifting amount of the threshold voltage (Vth) of the NMOS transistor TB of the shift register 100, and a dot line 402 raised along with the time represents shifting amounts of the threshold voltages (Vth) of the NMOS transistors T2 and T6 of the shift register 300.
According to the above description of FIG. 4, it is obvious that shifting amounts of the threshold voltages (Vth) of the NMOS transistors T2 and T6 of the shift register 300 flatly trend to the shifting amounts of the threshold voltages (Vth) of the NMOS transistors TB of the shift register 100. Therefore, the utilization reliability of the NMOS transistors T2 and T6 can be improved, and the capability that the NMOS transistors T2 and T6 pull down the voltage level of the scan signal On output from the shift register 300 to the low level gate voltage VGL is increased accordingly.
Though the shift register 300 of FIG. 3 can resolve the problem of the shift register 100, the NMOS transistors T2 and T6 used for pulling down the voltage level of the scan signal Gn output from the shift register 300 to the low level gate voltage VGL have to be respectively utilized together with the control units 301a and 301b, so that an layout area of the shift register 300 is increased a lot, which is of no avail to the increasing demand of narrow frame panels.